SOI (strained/unstrained Silicon-On-Insulator), SOS (Ultra Thin Silicon on Sapphire) and Nanotechnology - molecular level densities : Transistor/Gate level Design Software Bulk CMOS has run out of steam to continue to reduce supply voltage (geometry shrink does not lead to supply voltage reduction), which quite frankly has been the main method of reducing power for gate level design (multiple threshold voltage bulk CMOS cells (for leakage reduction) do not reduce the total power consumption (which is mainly dependent on supply voltage(s)), but barely give the illusion of reducing leakage power which is a small fraction of the overall power consumption anyway and the total leakage current still is appreciable for bulk-CMOS). SOI provides further potential of reducing supply voltage (current commercial SOI process is available down to 0.42volts supply). Increase battery life for low-power devices (lowest power SOI know to humankind), SOI wrist watch may not need a battery change in it's lifetime. Most multi-processor designs at high-end have been in SOI production already. This software specifically optimizes SOI/SOS from high level descriptions directly to transistor-level design to reduce floating body effects, etc. both for partially depleted and fully depleted devices, where gate delay keeps continuously varying over long periods of simulation time and direct port of bulk CMOS to SOI may lead to functional and/or timing failure. Bulk/Substrate tied to supply/ground is totally useless in SOI, due to high channel resistance, thus one is wasting area while trying to implement an existing bulk CMOS design without any change. SOI design for speed to market is a feast for the designer's heart to see superbly optimized transistor level designs, unachievable manually in any timely manner. Design in dynamic (with pre-charged intermediate nodes), static low-hysteresis transistor-level, ratioed (pseudo-nmos style SOI), Gate-Body Gate-Source contacted design, mux-style transistor-level design. Transistor level design approaches excel in SOI due to lower junction capacitances and thus a giving rise to a whole new high speed design approach. By choosing to utilize your old bulk CMOS gate design into SOI, you may loose all advantage over bulk CMOS to your competiton who may beat your unoptimized SOI design with their next bulk CMOS geometry shrink process itself. SOS additionally provides back-end optical coupling;Both SOI/SOS offer radiation-hardening for space, aircraft, satellite and defense electronics. Nanotubes provides molecular level geometries for ultra high density and our software provides for large and efficient decoder design, etc. for molecular Nanotechnology memories. Keep your lead and keep leading and enriching !! Available on Solaris & Level 57 and 58 Hpsice SOI models supported.